1. Field of the Invention
The present invention relates to an AD (analog-digital) converter, a physical quantity distribution detecting unit, and an imaging apparatus.
2. Description of the Related Art
For a physical quantity distribution detecting unit which detects the distribution of physical quantity, for example, there is a solid state imaging device which has unit pixels (unit sensors) two dimensionally arranged in a matrix, the unit pixel including a photoelectric conversion element which detects the light quantity of incident light. The solid state imaging device is roughly classified into an electric charge transfer solid state imaging device typified by a CCD (Charge Coupled Device) image sensor and an X-Y addressing solid state imaging device typified by a CMOS (Complementary Metal Oxide Semiconductor) image sensor.
In recent years, instead of the CCD image sensor which has been the mainstream before, attention is focused on the CMOS image sensor. This is because the CMOS image sensor overcomes various problems of the CCD image sensor, for example, the necessity of special processes for fabrication, the necessity of a plurality of power supply voltages for operation, and the necessity of combining a plurality of peripheral ICs for operation, leading to a very complicated system.
The CMOS image sensor has huge merits, for example, the same fabrication processes can be used as those for a typical CMOS integrated circuit that is produced all over the world, the CMOS image sensor can be driven by a single power source, and an analog circuit and a logic circuit using the CMOS processes can be mounted on the same chip to reduce the number of peripheral ICs.
In the CCD image sensor, its output circuit mainly uses a single channel output using an FD (Floating Diffusion) amplifier. However, the CMOS image sensor has an FD amplifier for every pixel, its output is mainly column parallel output in which pixels are two dimensionally arranged in a matrix to form a pixel array part, a certain row in the pixel array part is selected and the row is read at the same time in the column direction. This is because it is difficult to obtain sufficient drive performance by the FD amplifier arranged in the pixel, it is thus necessary to drop the data rate, and it is considered that parallel processing is advantageous.
For the signal output circuit of the parallel output CMOS image sensor, various configurations are designed. For one of the most cutting edge forms, a CMOS image sensor is known which is mounted with a column parallel AD converter device in which an AD converter is arranged for every column to take out a pixel signal as a digital signal (for example, see JP-A-2005-323331 (Patent Reference 1)).
In the CMOS image sensor mounted with the column parallel AD converter device, for the AD converter to be arranged at every column, such an AD converter is used in which an analog signal obtained from a unit pixel at every selected row through a column signal line is compared with a ramp wave reference voltage Vref by a comparator to convert the analog signal in the direction of the time base, and the time period is measured to convert the analog signal into a digital signal.
Here, in the CMOS image sensor mounted with the column parallel AD converter device, the comparator for use in the AD converter arranged at every column is considered.
FIG. 9 shows a typical circuit diagram depicting a two-input comparator. As shown in FIG. 9, the comparator is a differential amplifier comparator configured of differential pair transistors 101 and 102, active load transistors 103 and 104, and a constant current source transistor 105.
In the differential amplifier comparator, each of the gate terminals of the differential pair transistors 101 and 102 are an input terminal, and to the input terminal, a reference voltage Vref and a signal voltage Vx are inputted. The drain terminal of the transistor 101 in the differential pair transistors 101 and 102 is the output terminal of the comparator.
Generally, in the differential amplifier comparator, the polarity of output is reversed at the point at which the input voltage is crossed, but it is normal that the comparator has offset voltage at the crossing point due to variations in the transistor characteristics.
FIG. 10 shows the current characteristics of a typical transistor. In the typical transistor, a current Ids with square characteristics flows out from the point at which a gate-source voltage Vgs exceeds the threshold voltage. When there are variations in the transistor characteristics, the flowing currents have differences even though the same bias voltage is applied as indicated by characteristics S11 and S12. It is assumed that the transistor is unchanged and used as the differential pair transistors 101 and 102 for the comparator. Even though the same input voltage is reached, the polarity is not reversed as the comparator because the current characteristics have differences, the current value is not the same until a certain voltage difference appears, and then the polarity can be reversed as the comparator. The voltage difference necessary for the reversal is a so-called input voltage offset, which exits in any differential amplifiers more or less.
Heretofore, in the CMOS image sensor mounted with the column parallel AD converter device, a scheme is made so that the offset of the comparator does not directly lead to the error of AD conversion accuracy. More specifically, AD conversion is performed twice, at a first time and a second time, and a subtraction process is finally performed for CDS (Correlated Double Sampling), whereby the error components similarly occurring at the first time and the second time are cancelled for complete removal. Therefore, when the offset of the comparator occurs by the same amount at the first time and the second time, the offset is completely cancelled by the subtraction process, causing no problem.
A problem for considering the precondition is the back bias effect of a transistor. In the conversion at the first time, the range that the signal possibly takes is considerably limited since the reset level of the unit pixel is read, but in the conversion at the second time, the range that the signal possibly takes is wide since the signal depending on the incident light quantity is read, and the value can be taken that is separated from the value at the first time.
FIG. 11 shows the outline of the operation. Since the ranges that the signal possibly takes are different in the conversions at the first time and the second time, the reverse points (common mode voltage) are greatly different as the comparator.
Returning to FIG. 10, this situation is considered in the current characteristics. Since the back gate of the differential pair transistors 101 and 102 is grounded, the difference of input voltage directly appears as the back bias effect.
The threshold voltage of the transistor is greatly changed due to the back bias effect. As indicated by the characteristics S11 and S12, when the transistor characteristics have variations, variations naturally occur in the way to apply the back bias effect. Consequently, the offset of the comparator voltage in the conversions at the first time and the second time is to vary. This is a huge problem because it directly affects the AD conversion characteristics.
Since the comparator is common for the pixel for every column, the problem appears as the conversion error in vertical streaks depending on the brightness in an image. Particularly, it becomes the conversion error in vertical streaks depending on the incident light quantity (output signal amount). The vertical streaks are categorized as conspicuous ones as error. Since the vertical streaks occur depending on the output signal amount, it is difficult to correct the streaks by digital signal processing, which are a huge problem.